Compared to silicon (Si), compound semiconductor materials offer several advantages with regard to device performance which makes them attractive for use in high-power and high-frequency electronics. For example, high band-gap compound materials such as silicon carbide (SiC) or gallium arsenide (GaN) have a high breakdown field strength and high critical avalanche field strength. Accordingly, the doping of the semiconductor regions can, in comparison to silicon semiconductor regions, be higher at given rated blocking voltage. This reduces the on-state resistance Ron of the device. Other compound semiconductor materials such as indium phosphide (InP) offer a much higher electron mobility than silicon. Accordingly, compound semiconductor devices with higher switching speeds and/or lower on-state resistance Ron may be provided.
For manufacturing semiconductor devices, for example power devices, suitably adapted semiconductor substrates are needed. For cost reasons, semiconductor devices are preferably manufactured on large wafers. However, larger monocrystals of compound semiconductor materials and monocrystalline compound wafers of more than about 8″ in diameter, respectively, are either not available or very expensive.
Other approaches use a layer of the compound semiconductor material formed on a substrate wafer by epitaxy. However, due to the different crystal lattices, mechanical stress typically occurs during processing. This may, for example, result in wafer bowing. The mechanical stress may even have an impact on the performance of the devices to be manufactured. For example, the crystal quality of the epitaxially formed compound semiconductor layer may be affected. Furthermore, larger substrate wafers that are adapted to the compound semiconductor material with respect to their crystal lattice and thermal properties are typically also very expensive.
In view of the above, there is a need for improvement.